High-Speed PCB Design: Layout, Routing & Signal Integrity

Table of Contents

Chapter 1: PCB Routing

In PCB design, routing is a critical step in completing the product layout—one could say that all prior preparation is for this stage. Among all aspects of a PCB, the routing process demands the highest level of precision, the finest techniques, and the greatest amount of work. There are single-sided, double-sided, and multi-layer PCB routing. Routing can be done in two ways: autorouting and interactive routing. Before running autorouting, you can use interactive routing to pre-route nets with strict requirements. Input and output edge traces should avoid parallel adjacency to prevent reflection interference. If necessary, add ground isolation. Traces on two adjacent layers should be perpendicular to one another, since parallelism can lead to parasitic coupling.

The throughput rate of autorouting relies on a good component placement. Routing rules can be predefined, including the number of bends per trace, the number of vias, the number of route segments, and so on. Generally, one begins with exploratory “rat’s nest” routing to quickly connect short traces, and then proceeds to maze-type routing—optimizing each net’s overall path globally. Maze routing can break existing routes if needed and attempt re-routing to improve the overall result.

With today’s high-density PCB designs, through-hole vias (THVs) are often inadequate: they consume many precious routing channels. To resolve this, blind and buried via technologies have emerged. These vias not only serve the same connectivity function as through-hole vias but also free up many routing channels, making routing more convenient, fluid, and efficient. The process of PCB design is at once complex and straightforward; truly mastering it requires hands-on experience by a broad range of electronic design engineers to internalize its essence.

1. Power and Ground Routing

Even if all signal routing on a PCB is executed perfectly, inadequate handling of power and ground nets can introduce noise and interference that degrade performance or even jeopardize product yield. Therefore, power and ground routing must be treated with utmost care, minimizing noise and interference to ensure product quality.

Every electronic design engineer understands that noise between power and ground buses arises from multiple causes. Below are measures to suppress such noise:

1. Decoupling Capacitors
   It is well known that placing decoupling capacitors between power and ground helps filter high-frequency noise.

2. Wider Power and Ground Traces
   Make power and ground traces as wide as possible—ideally, ground traces should be wider than power traces, which in turn should be wider than signal traces. Typically, signal trace widths range from 0.2 mm to 0.3 mm, with minimum widths down to 0.05 mm–0.07 mm. Power traces are usually 1.2 mm–2.5 mm wide.
   For digital PCBs, you can create a ground plane loop using wide ground conductors (forming a ground mesh). (Note: analog circuits generally should not use a wide ground mesh in this way.)

3. Copper Pour for Ground Plane
   Use a large copper pour as a ground plane. Connect all unused board areas to ground. Alternatively, make a multi-layer board where one layer is dedicated to power and another to ground.

2. Managing Mixed-Signal (Digital and Analog) Grounding

Many modern PCBs are not purely digital or purely analog but contain a mix of both. When routing, you must consider mutual interference—especially noise on the ground net. Digital circuits operate at high frequencies, while analog circuits are highly sensitive. For signal traces, route high-speed digital lines as far away as possible from sensitive analog components. Regarding grounding, the PCB has only one external ground node, so internally you must separate digital and analog grounds. Within the board, digital ground and analog ground are kept physically separate and do not connect to each other except at a single point at the interface to the outside world (e.g., at connectors). If you do connect digital and analog grounds on the PCB itself, ensure there is only one connection point. In some systems, you may choose not to tie them together on the board at all—this decision is determined by the overall system design.

3. Routing on Power (or Ground) Planes

In multi-layer PCB routing, once signal layers become congested and you consider adding more layers, the cost and complexity increase. To avoid this, you can sometimes route signals on power or ground planes. First consider using the power plane for routing; only if that is not feasible should you use the ground plane. Preserving the integrity of the ground plane is generally preferable.

4. Handling Component Leads in Large Copper Areas

When you have large copper areas—especially ground or power planes—components’ leads must connect to these planes. From an electrical standpoint, it is best for a component’s lead pad to be fully surrounded by copper. However, when soldering, a full copper surround can create problems:
  • It may require high-power soldering tools.
  • It may lead to cold or weak solder joints.

To balance electrical performance and manufacturing considerations, use “thermal relief” (often called a “thermal pad”) on component pads within copper pours. A thermal pad is shaped like a cross (or plus sign) so that during soldering, the pad does not dissipate heat too quickly into the plane, reducing the chance of a cold joint. Handling component lead pads in the power (or ground) planes of a multi-layer board is done in the same way.

5. The Role of the Net Grid System in Routing

In many CAD systems, routing is guided by a grid or mesh system. If the grid is too fine, you gain many potential routing channels, but the step size is tiny and the graphical data becomes large—demanding more storage and slowing computer performance. Furthermore, some channels are ineffective: they may be blocked by component pads, mounting holes, or mechanical drill holes. If the grid is too coarse, there are too few routes and the routing success rate plummets. Therefore, you need a reasonably dense grid system to support routing.

Standard through-hole components have a pin spacing of 0.1 inch (2.54 mm). As a result, grid spacings are typically set to 0.1 inch (2.54 mm) or integer subdivisions thereof, such as 0.05 inch, 0.025 inch, 0.02 inch, and so on.

6. Design Rule Check (DRC)

After completing routing, you must carefully verify that the routed design complies with all predefined rules. At the same time, confirm that those rules align with PCB manufacturing process requirements. Typical DRC items include:

1. Clearances
   Check spacing between trace-to-trace, trace-to-pad, trace-to-via, pad-to-via, and via-to-via. Ensure they meet manufacturing requirements.

2. Power and Ground Trace Widths
   Verify that power and ground traces are wide enough, and that the coupling between power and ground is sufficiently tight (low impedance). Check for any remaining opportunities on the PCB to widen ground traces.

3. Critical Signal Nets
   For critical nets, ensure best practices were applied—for example, minimize length, add guard traces, and keep input and output nets well separated.

4. Separate Grounding for Analog and Digital Sections
   Confirm that analog and digital sections each have their own ground (unless a deliberate single-point connection was designed).

5. Silkscreen (Overlay) Checks
   Verify that added graphics (logos, reference designators, etc.) do not short signal nets. Ensure silkscreen does not overlap pads in a way that could interfere with soldering.

6. Refine Suboptimal Trace Geometries
   Modify any poorly shaped or jagged traces.

7. Manufacturing Aids
   Check if your PCB requires tooling strips, fiducials, test points, etc. Verify that solder mask clearances follow manufacturing guidelines and that text/legends do not cover exposed pads.

8. Multi-Layer Power/Ground Plane Borders
   Ensure that the copper plane edges (power or ground) are inset from the board outline. Exposed copper foil at the board edge can lead to shorts.

Chapter 2: PCB Component Placement

In PCB design, placement is a crucial step. The quality of the placement directly affects routing efficiency. Therefore, one can assert that a good placement is the first step toward successful PCB design.

There are two placement methods: interactive placement and autorouting-based placement (sometimes called automatic placement). Typically, you begin with autorouting-based placement and then refine it interactively. As you place components, you can refer to anticipated routing needs to reassign logic gates or swap gate locations—for example, exchanging two gate circuits—to achieve a placement that is optimal for routing. Upon completing placement, update the corresponding netlist and any related information back onto the schematic so that the PCB data matches the schematic and future documentation or design modifications remain synchronized. Also, update any analog-related information so that board‑level electrical and functional verification can be performed.

– Consider Overall Aesthetics
A product’s success depends not only on internal quality but also on its overall aesthetic. Both must be excellent for a product to be deemed truly successful.
On a PCB, component placement should be balanced in density and arranged in an orderly way—avoid placing too many components in one area or having one end of the board overly crowded.

– Placement Review Checklist
  • Does the PCB outline match the manufacturing drawings? Can it comply with PCB fabrication requirements? Are fiducials or alignment marks present?
  • Are there any 2D or 3D placement conflicts between components?
  • Is the placement density uniform and orderly? Are all components placed?
  • Can frequently replaced components be accessed easily? Are plug‑in daughter boards easy to insert or remove?
  • Are heat‑sensitive components placed at a safe distance from high‑power or heat‑generating parts?
  • Can adjustable (trim) components be easily accessed for tuning?
  • In areas needing heatsinks, is a heatsink mounted? Is airflow adequate?
  • Is the signal flow logical and are net lengths minimized?
  • Are connector placements compatible with the mechanical enclosure?
  • Have potential signal interference or crosstalk issues been addressed?

Chapter 3: High-Speed PCB Design

(1) Challenges in Electronic System Design

As system complexity and integration scale have grown, electronic designers are now working with circuits operating above 100 MHz; bus frequencies have reached or exceeded 50 MHz, with some systems surpassing 100 MHz. Currently, roughly 50 % of designs clock above 50 MHz, and nearly 20 % exceed 120 MHz.
When a system runs at 50 MHz, transmission‑line effects and signal integrity issues arise. At 120 MHz, traditional PCB design methods become ineffective unless high‑speed design techniques are used. Thus, high‑speed circuit design techniques have become indispensable for electronic system designers. Only by employing high‑speed design methods can the design process be controlled. Controlled means reliable—and only reliable designs succeed.

(2) What Constitutes a High-Speed Circuit

Typically, when a digital logic circuit’s clock frequency reaches or exceeds 45 MHz–50 MHz and such high‑frequency sections occupy a significant portion of the system (for example, one‑third), it is considered a high-speed circuit.
In reality, the harmonic frequencies of a signal’s edges are far higher than the fundamental frequency. Fast signal edges (the rising and falling transitions) give rise to unexpected transmission effects. Commonly, if the line’s propagation delay is greater than one‑half the driver’s signal rise time, that net is regarded as a high-speed or transmission‑line net.
Signal transmission occurs during state changes (rising or falling edges). If the propagation delay from driver to receiver is less than half the rise time, any reflected wave will arrive back at the driver before the signal has finished switching. If the reflection is large enough, its superposition may alter the logic state. Conversely, if propagation delay exceeds half the rise time, reflections arrive after the signal transition, causing less distortion.

(3) Identifying High-Speed Signals

We have defined the condition for transmission‑line effects, but how do you know if a given net’s delay exceeds half the driver’s rise time? Typically, a device’s datasheet provides its rise‑time parameter. On the PCB, the propagation delay is determined by the actual trace length. For reference, PCB trace delay is approximately 0.167 ns per inch. However, additional factors—such as multiple vias, many component pins, or numerous net constraints—can increase delay. High-speed logic devices often have rise times around 0.2 ns. For GaAs devices, the maximum trace length on the board is about 7.62 mm (0.3 inch).
Let Tr be the signal rise time and Tpd be the trace propagation delay.
  • If Tr ≥ 4 × Tpd, the signal is in the safe region.
  • If 2 × Tpd ≤ Tr < 4 × Tpd, the signal is in the marginal region.
  • If Tr < 2 × Tpd, the signal is in the problem region.
Nets in the marginal or problem regions require high-speed routing techniques.

(4) What Is a Transmission Line

A PCB trace can be modeled as a series and parallel combination of capacitance, resistance, and inductance, as shown below:

• A series resistance (typical 0.25–0.55 Ω/ft, depending on dielectric material) is in series with each segment of the trace.

• A parallel conductance (usually very high impedance) represents leakage through the dielectric.

When you add these parasitic elements to a trace, the final impedance of the trace is called its characteristic impedance (Z₀). Wider traces, traces closer to a power or ground reference, or higher‑dielectric‑constant substrates all reduce Z₀. If a transmission line is not matched to its receiver impedance, current signals and their final steady states differ—causing reflections. Those reflections then travel back toward the driver, potentially bouncing several times until the energy dissipates and the voltage/current stabilize. This phenomenon manifests as ringing on rising or falling edges.

(5) Transmission-Line Effects

Given the transmission‑line model above, these are the key effects encountered:

  • Reflected Signals
    If a trace is not properly terminated (matched at its end), drive‑side pulses will reflect at the receiver. Large reflections distort the waveform, causing logic errors or design failures. Distorted waveforms are also more susceptible to noise, risking system malfunction. Poor termination also increases EMI, which can not only degrade the design in question but also disrupt nearby electronics.
    Causes of Reflection: traces that are too long; unterminated lines; excessive capacitance or inductance; impedance mismatch.

  • Delay and Timing Errors
    Excessive trace delay can cause timing violations—signals may remain between logic thresholds too long, causing functional errors. This is especially problematic when multiple receivers share a net. Designers must calculate the worst-case delay to ensure timing correctness.
    Causes: driver overloading; overly long traces.

  • Multiple Crossings of Logic Thresholds (Hunt‑Oscillation)
    A changing signal may cross a logic threshold multiple times while ringing, leading to false switching. This is a form of oscillation around the logic threshold.
    Causes: long traces; unterminated lines; excessive capacitance or inductance; impedance mismatch.

  • Overshoot and Undershoot
    Overshoot and undershoot arise from excessively long traces or very fast edges. While many device inputs have clamp diodes to protect against moderate excursions, large overshoots/undershoots can exceed power rails, damaging components.

  • Crosstalk (Induced Noise)
    When a signal toggles on one trace, adjacent traces can pick up induced signals. Crosstalk magnitude is smaller when traces are farther from each other or farther from ground. Asynchronous signals and clock nets are especially prone to causing crosstalk. Mitigation: separate aggressive signal nets or shield sensitive nets with ground traces.

  • Electromagnetic Interference (EMI)
    EMI refers both to conducted and radiated emissions and to susceptibility. A powered digital circuit radiates electromagnetic waves, potentially interfering with nearby electronics. Main causes: high switching frequency and poor layout/routing. While EMI simulation tools exist, they are expensive and require complicated parameter/boundary‑condition setup, which can reduce accuracy and practicality. The most common approach is to apply EMI‑control design rules at every stage—ensuring each design step enforces and checks compliance.

(6) Methods to Avoid Transmission-Line Effects

To address the issues above, consider the following strategies:

6.1 Strictly Control Critical Net Lengths
  For any net with fast edges, always account for transmission-line effects on the PCB. Modern high-speed ICs often demand this. Some guidelines:
  - For CMOS or TTL designs operating below 10 MHz, route lengths should not exceed 7 inches.
  - For designs at 50 MHz, route lengths should not exceed 1.5 inches.
  - For designs at 75 MHz or higher, route lengths should not exceed 1 inch.
  - For GaAs devices, the maximum route length is 0.3 inch.
  Exceeding these guidelines risks incurring transmission-line issues.

6.2 Plan Appropriate Routing Topologies
  Another way to mitigate transmission-line effects is to choose the proper routing topology and termination scheme. A net’s topology refers to the order in which you route branches and stubs. When using high-speed logic, unless each branch is very short, fast edges on a trunk line will be distorted by stubs. The two most common topologies are daisy‑chain and star.
  - Daisy‑Chain Routing: Traces run from the driver to each receiver in series. If you use a series resistor for impedance matching, place it as close to the driver as possible. Daisy‑chain excels at controlling high‑order harmonics but has the lowest routing success rate and can be hard to achieve 100 % routing. In practice, try to keep stub lengths as short as possible. A safe guideline is:
    Stub Delay ≤ 0.1 × Trt,
    where Trt is the receiver’s rise time. For high-speed TTL, stub lengths should be under 1.5 inches. This topology uses less routing area and allows a single resistor for termination, but receiver timing will be skewed.
  - Star Topology: A central driver fans out to each receiver with individual branches. This effectively eliminates skew. However, on dense PCBs, manually routing a star is very difficult. Autorouters are best for star topologies. Each branch needs its own termination resistor matched to the trace’s characteristic impedance. You can calculate Z₀ and termination resistance manually or let CAD tools compute them.

  In the examples above, simple series resistors are used. In practice, you can choose more sophisticated terminators:
  - RC Terminators: Good for reducing power consumption but suitable only where the signal is relatively stable. RC terminators work best on clock nets. Their downside is that the added capacitance can alter the signal shape and speed.
  - Series‑Resistor Terminators: Do not consume extra power but slow down the signal slightly. Use these where timing margins are sufficient, such as on general‑purpose bus drivers. Their advantage is fewer components and lower routing density.
  - Split (Thevenin) Terminators: Place two resistors near the receiver to form a voltage divider. This does not load the signal and effectively reduces noise. It is common on TTL inputs (ACT, HCT, FAST).

  Finally, consider terminator packaging and mounting: SMD (surface‑mount) resistors have lower parasitic inductance than through-hole parts, making them the preferred option. If you must use through-hole resistors, you can mount them vertically or horizontally. Vertically mounted resistors have a shorter lead to the board, reducing thermal resistance and allowing heat to dissipate more easily. However, a taller vertical resistor increases parasitic inductance. Horizontally mounted resistors have lower inductance but, if overheated, can drift and eventually fail open, causing termination to fail.

6.3 Suppressing Electromagnetic Interference (EMI)
  Solving signal integrity issues goes hand in hand with improving a PCB’s electromagnetic compatibility (EMC). Ensuring a good ground system is critical. For complex designs, dedicating one signal layer and one ground layer is very effective.
  Also, keep the routing density on outer signal layers as low as possible to reduce radiation. You can achieve this by using “build-up” or “surface‑isolation” techniques: build up thin insulation layers and micro‑vias on top of a standard PCB. Resistive and capacitive elements can be embedded under the surface, effectively doubling routing density per unit area. Reducing PCB area significantly affects routing topology—shorter current loops and shorter stub lengths—which reduces EMI (radiation is roughly proportional to loop area). Smaller board size also allows for high‑pin‑count, fine‑pitch devices, further reducing trace lengths and loop areas, enhancing EMC.

6.4 Other Techniques
  - To minimize voltage spikes on IC power pins, add decoupling capacitors directly at each IC’s power pin rather than only on the power plane. This more effectively smooths out transients, which is why some sockets include decoupling capacitors or specify that the capacitor be placed very close to the device.
  - Group any high-speed or high‑power ICs close together to reduce voltage transients on the power plane.
  - If no dedicated power plane exists, a long power trace can create large loop areas between signal and return paths, acting as an antenna (both transmitting and receiving).
  - A “proper” loop is one that does not pass through any net or other traces; a “cut” or “cross” loop crosses another trace or net, forming a closed antenna loop. Both scenarios cause EMI. Closed loops are especially problematic because radiation is roughly proportional to loop area.

Conclusion

High-speed circuit design is a highly complex process. Zuken’s high-speed routing algorithm (Route Editor) and EMC/EMI analysis tools (INCASES, Hot‑Stage) are used to analyze and identify issues. The methods described here are specifically geared toward solving high-speed design challenges. Moreover, many factors in high-speed design can be contradictory—for instance, placing high-speed devices close together reduces delay but can increase crosstalk and heat density. In designing a high-speed PCB, you must balance all factors, making comprehensive trade‑offs to meet performance requirements while managing complexity. Employing proper high-speed PCB design techniques makes the process controllable. Only controllable designs are reliable—and only reliable designs succeed.